Unlike conventional dynamic random access memories (DRAMs), next-generation memory devices may be nonvolatile and may not require a refresh operation to maintain the data stored therein. Research on memory devices has focused on increasing data storage capacity and decreasing power consumption. Some next-generation memory devices currently being researched include a PRAM (Phase-change Random Access Memory) formed of phase change material, an RRAM (Resistance Random Access Memory) formed of material having properties of variable resistance, and an MRAM (Magnetic Random Access Memory) formed of a ferromagnetic material.
In the next generation memory devices, the PRAM employs phase change material as a storing medium. The phase change material may include a material, such as a chalcogenide, in which a phase of the material is changed in response to a temperature change. Changing the phase of the material may also change the resistance of the material. A material such as GexSbyTez (hereinafter, referred to as ‘GST’) may be used as the phase change material (GST being an alloy of germanium, antimony and tellurium).
A phase change material that can be used for semiconductor memory devices is capable of being quickly changed between an amorphous state and a crystalline state.
The phase change material has a high resistance in the amorphous state and has a low resistance in the crystalline state. Thus, the amorphous state may be defined as a reset state RESET or logic ‘1’ and the crystalline state for the phase change material may be defined as a set state SET or logic ‘0’, or vice versa, in its application to the semiconductor memory devices.
PRAM memory cells may be classified into a transistor structure and a diode structure. In the transistor PRAM structure, a memory cell structure including phase change material is coupled in series to an access transistor. In the diode structure, a memory cell structure including phase change material is coupled in series to a diode. An example of a PRAM including memory cells of the transistor and diode structure is disclosed in U.S. Pat. No. 6,760,017.
As compared with the PRAM employing the transistor structure, the PRAM employing the diode structure may have the advantage of applying a write current that increases exponentially in response to an applied voltage. Furthermore, the diode structure may not be subject to the same size limitations as transistor structures. Thus, it may be possible by using the diode structure to reduce memory cell and/or overall chip size. Thus, the use of PRAM devices having memory cells of a diode structure is expected to increase in semiconductor memory devices requiring high integration, high speed and/or low power consumption.
FIG. 1 illustrates a memory cell of a diode structure in a general PRAM device.
Referring to FIG. 1, a memory cell 50 in the PRAM includes a diode D and a variable resistance device R. The variable resistance device R may include a phase change material as described above.
The diode D of the memory cell 50 is coupled between a word line WL and the variable resistance device R. A cathode terminal of the diode D is coupled to the word line WL, and an anode terminal of the diode D is coupled to one end of the variable resistance device R. Another end of the variable resistance device R is coupled to a bit line BL.
In the semiconductor memory device employing a memory cell of the diode structure described above, the variable resistance device R is provided as a data storage element, and a write operation using a reversible characteristic of the variable resistance device R is performed according to a magnitude of current and voltage source applied to the memory cell through the bit line BL. In other words, in performing the write operation to the memory cell 50, current is supplied through the bit line BL, and a voltage on the word line WL is set at low level or ground level. Thus, a forward bias is applied to the diode D and a current path is formed from the bit line BL to the word line WL. In response, a phase change is generated in the variable resistance device R which causes the variable resistance device R to become ‘set’ (e.g. to a low resistance state) or ‘reset’ (e.g. to a high resistance state).
In a read operation, data may be read according to the amount of current flowing through the memory cell and according to the state of the memory cell (i.e. whether the cell is in a ‘set’ or ‘reset’ state). When the variable resistance device R within the memory cell is in a ‘reset’ state, the memory cell has a high resistance value, so that a relatively small quantity of current flows in response to a constant voltage level applied to the bit line BL. When the memory cell is in a ‘set’ state, the memory cell has a low resistance value, so that a relatively large amount of current may flow.